1. Field of the Invention
The present invention relates to the field of packaging for electrical components. In particular, the present invention relates to an assembly of components that support high bandwidth data transfer rates.
2. Description of Art Related to the Invention
For many years, electronic systems have been designed to include one or more circuit boards. Each circuit board features one or more transmission lines either routed on its surface or integrated between selectively patterned insulation and metal layers of the circuit board. Electronic hardware is placed on the surface of the circuit board and is appropriately connected to various transmission lines which provide signal communications and power.
One standard technique used for packaging components, particularly conventional dynamic random access memory (DRAM), is the use of horizontal chip-scale packages (CSPs). Horizontal CSPs offer a number of architectural advantages due to their small physical dimensions. For example, horizontal CSPs possess a low package inductance and may be arranged to meet minimum spacing constraints between integrated circuit (IC) devices. The reduction in spacing between components causes a lower impedance to be realized over the signal transmission lines used to connect the components. This lower impedance enhances the integrity of signals transmitted across these transmission lines.
Unfortunately, horizontal CSP technology does not provide optimal memory density and operating frequency for Direct Rambus DRAM (RDRAM.RTM.) designed by Rambus, Inc. of Mountain View, Calif. RDRAM.RTM. includes an interface for a high-speed interconnect in order to achieve high bandwidth data transfer rates. For example, conventional horizontal CSP packages can be as wide as twelve (12) millimeters (mm). This maximum CSP package size, combined with a spacing requirement of 2.5 mm between components on the same side of the circuit board to allow clearance for manufacturing and assembly, would result in an effective component pitch of 7.25 mm when components are placed on opposite sides of a circuit board. This pitch is too large for placement of thirty-two (32) RDRAMs on a single communication channel to achieve maximum operating frequency within a standard computer chassis. An optimal pitch spacing of approximately 2.5 mm would be necessary for electrical considerations and to implement a thirty-two (32) device communication channel with maximal operating frequency within existing computer chassis designs.
In addition, it is common practice to develop new components using larger die size technology. Over time, as the ICs designs are refined and improved, they are placed on smaller die size technology. This is done to reduce the package size in order to minimize the amount of circuit board surface area occupied by that package. For a horizontal CSP, as the die size is adjusted, the electrical effects on the signal transmission lines would also need to be adjusted because the length of the transmission lines would increase. This may require the chip layout for the circuit board to be modified as smaller die size technology is used or to risk adverse effects caused by enhanced impedance on the longer transmission lines.
Therefore, it is desirable to develop an IC assembly that uses a different packaging solution to overcome the disadvantages described above.